RT8073
Pin Configurations
(TOP VIEW)
COMP
GND
EN
VIN
2
3
4
8
FB
RT
LX
BOOT
PGND
9
7
6
5
COMP
PGOOD
SS
EN
VIN
VIN
1
2
3
4
5
6
13
12
11
10
9
8
7
FB
RT
LX
LX
LX
BOOT
SOP-8 (Exposed Pad)
WDFN-12L 3x3
Functional Pin Description
Pin No.
SOP-8
(Exposed Pad)
1
2
3
4
5
6
7
8
9
WDFN-12L 3x3
1
--
4
5, 6
7
8, 9, 10
11
12
13
(Exposed Pad)
Pin Name
COMP
GND
EN
VIN
BOOT
LX
RT
FB
PGND
Compensation Node.
Analog Ground.
Chip Enable. Externally pulled high to enable and pulled low to
disable this chip, and it is internally pulled up to high when the
pin is floating.
Power Input.
Bootstrap Supply for High Side Gate Driver.
Switch Node.
Frequency Setting.
Feedback Voltage Input.
Power Ground. The exposed pad must be shouldered to a
large PCB and connected to PGND for maximum power
dissipation.
Power Good Indicator with Open Drain Output. It is high
impedance when the output voltage is regulated. It is internally
pulled low when the chip is shutdown, thermal shutdown or
VIN is under UVLO threshold.
Soft-Start Control.
Pin Function
--
2
PGOOD
--
3
SS
Copyright
©
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
PGND
DS8073-01
November 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
