RT8015D
Function Block Diagram
SHDN/RT
SD
ISEN
OSC
COMP
0.8V
FB
Output
Clamp
OC
Limit
Slope
Com
PVDD
EA
Int-SS
0.9V
0.7V
POR
0.2V
Control
Logic
Driver
LX
NISEN
NMOS I Limit
PGND
PGOOD
V
REF
OTP
GND
VDD
Layout Guide
Place the input and output
capacitors as close to the
IC as possible.
V
IN
C
IN
GND
C
OUT
V
OUT
LX should be
connected to Inductor
by wide and short
trace, keep sensitive
L1 components away
from this trace
R3
C1
GND
Bottom Layer
R4
PVDD
VDD
PGOOD
FB
COMP
6
7
8
9
10
RT8015D
5
4
3
2
1
PGND
LX
LX
GND
SHDN/RT
R
OSC
C
F
R1
R2
R
COMP
C
COMP
GND
V
OUT
Place the feedback and
compensation components as
close to the IC as possible.
DS8015D-02 March 2011
www.richtek.com
3