RT8032
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the
trapezoidal current at the source of the top MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
−
T
A
) /
θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the
θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8032, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance
θ
JA
is layout
dependent. For WDFN-12L 4x3 packages, the thermal
resistance
θ
JA
is 60°C/W on the standard JEDEC 51-7
four layers thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by following
formula :
P
D(MAX)
= (125°C
−
25°C) / (60°C/W) = 1.667W for
WDFN-12L 4x3
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance
θ
JA
. For RT8032 package, the Figure 2 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation allowed.
1.8
V
I
RMS
=
I
OUT(MAX) OUT
V
IN
V
IN
−
1
V
OUT
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple,
ΔV
OUT
, is determined by :
⎡
1
⎤
Δ
V
OUT
≤ Δ
I
L
⎢
ESR
+
8fC
OUT
⎥
⎣
⎦
The output ripple is highest at maximum input voltage
since
ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
DS8032-02 March 2011
Maximum Power Dissipation (W)
Four Layers PCB
1.6
1.4
WDFN-12L 4x3
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curves for RT8032 Package
www.richtek.com
9
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
