ZULU
Pin Description (continued)
Pin No
Name
P0.3
Direction
D In / Out
or A In
Description
Port 0.3 See RF50 Port I/O section for complete descrip-
tion
XTAL2
9
A Out
External Clock Output. This pin is the excitation driver for
an external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
See RF50 Oscillator section for complete details.
Port 0.2. See RF50 Port I/O Section for a complete de-
scription.
External Clock Input. This pin is the external oscillator re-
turn for a crystal or resonator.
See RF50 Oscillator section.
Port 0.0. See RF50 Port I/O section for a complete de-
scription.
External VREF Input.
Internal VREF Output. External VREF decoupling capaci-
tors are recommended.
See RF50 Voltage Reference section.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15
µs.
A 1–5k pull-up to
VDD_MCU is recommended. See Reset Sources section
for a complete description.
Clock signal for the C2 Debug Interface
Port 2.7. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be config-
ured as an analog input. See RF50 Port I/O section for a
complete description.
Bi-directional data signal for the C2 Debug Interface.
D In
A In
P0.2
10
D In/Out
or A In
A In
XTAL1
P0.0
D In/Out
or A In
AI
AO
11
VREF
RST
12
C2CK
P2.7
13
C2D
14
16
P2.6
Vcc
D In / Out
or A In
In
D In/Out
D In/Out
Port 2.6.
See RF50 Port I/O section for a complete description.
Positive power supply, 1.8 to 3.6 V.
DS-ZULU-1
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