欢迎访问ic37.com |
会员登录 免费注册
发布采购

RF2483_1 参数 Datasheet PDF下载

RF2483_1图片预览
型号: RF2483_1
PDF下载: 下载PDF文件 查看货源
内容描述: 低噪声双频段正交调制器,带有AGC [LOW NOISE DUAL-BAND QUADRATURE MODULATOR WITH AGC]
分类和应用:
文件页数/大小: 28 页 / 753 K
品牌: RFMD [ RF MICRO DEVICES ]
 浏览型号RF2483_1的Datasheet PDF文件第4页浏览型号RF2483_1的Datasheet PDF文件第5页浏览型号RF2483_1的Datasheet PDF文件第6页浏览型号RF2483_1的Datasheet PDF文件第7页浏览型号RF2483_1的Datasheet PDF文件第9页浏览型号RF2483_1的Datasheet PDF文件第10页浏览型号RF2483_1的Datasheet PDF文件第11页浏览型号RF2483_1的Datasheet PDF文件第12页  
RF2483  
Pin  
1
Function  
VCC3  
Description  
Supply for RF output circuits.  
Interface Schematic  
VCC3  
RF Output  
Amplifier  
Supply for modulator and biasing circuits.  
2
3
VCC2  
VCC2  
VCC2  
Modulator and  
VGA  
In phase I channel positive baseband input port. Best performance is  
achieved when the ISIGP and ISIGN are driven differentially. The recom-  
ISIG P  
mended CW differential drive level (V  
-V  
) is 800mV  
.
ISIGP ISIGN  
P-P  
This input should be DC-biased at 1.2V±0.05V. The common-mode DC  
coltage on the ISIGP and ISIGN input signals is used to bias the modulator.  
In sleep mode an internal FET switch is opened, the input goes high imped-  
ance and the modulator is de-biased. The input impedance is typically  
5.5kΩ at low frequencies and at higher frequencies can be modeled as  
50Ω in series with 12pF to ground.  
V C C 2  
Phase or amplitude errors between the ISIGP and ISIGN signals may result  
in the even order distortion of the modulation in the output spectrum.  
DC offsets between the ISIGP and ISIGN signals will result in increased car-  
rier leakage. Small DC offsets may be deliberately applied between the  
ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel out LO leakage. The opti-  
mum corrective DC offsets will change with mode, frequency and gain con-  
trol.  
5 0  
Ω
1 2 p F  
Common-mode noise on the ISIGP and ISGN should be kept low as it may  
degrade the noise performance of the modulator.  
Phase offsets may be applied between the I and Q channels to improve the  
sideband suppression performance.  
In phase I channel negative baseband input port. See ISIGP.  
4
5
6
ISIG N  
ENABLE  
VCC1  
V C C 2  
5 0  
Ω
1 2 p F  
Enables power to the device.  
CMOS input.  
Logic 1 (1.4V to VCC)=Enabled.  
Logic 0 (0V to 0.5V)=Powered Down.  
V
C
C 2  
Supply for the LO buffers and quadrature network.  
VCC1  
The sideband suppression is a function of the VCC1 voltage. The inclusion  
of R3 (39Ω) lowers the voltage on VCC1 by around 400mV and results an  
improvement in sideband suppression but around a 0.2dB increase in  
noise at 20MHz offset.  
LO Quadrature  
Generator and  
Buffers  
GND1  
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical  
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.  
8 of 28  
Rev A8 DS060203