Preliminary
RF2162
Application Schematic - US CDMA
VCC
10 nF
Bypassing for VCC
100 pF
100 pF
2nd Harmonic Trap
2
Interstage tuning for centering
frequency response
TL3
100 pF
27 nH*
1 nH
1.8 nH
TL4
1
2
3
4
5
16
15
14
13
12
1 pF
100 pF
100 pF
TL2
TL1
To Vary Gain
11
RF OUT
330
Ω
100 pF
15 nH
9.1 pF**
5.1 pF**
RF IN
10
Matching network for
optimum load impedance
6
7
8
9
Matching network for
optimum input return loss
0
Ω
10 nH
100 pF
Bias Return
0
Ω
100 pF
Bypassing for
VREG1 and VREG2
VREG
1 k
Ω
VMODE
* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).
2-208
Rev A17 011011