Preliminary
RF2161
Pin
1
Function Description
Interface Schematic
Power supply for second stage and interstage match. Pins 1, 15 and 16
should be connected by a common trace where the pins contact the
printed circuit board.
VCC2
GND2
VCC1
RF IN
Ground for second stage. For best performance, keep traces physically
short and connect immediately to ground plane. This ground should be
isolated from the backside ground contact.
2
3
4
Power supply for first stage and interstage match. V should be fed
See pin 4.
CC
2
through a 1.2nH inductor terminated with a 8.2pF capacitor on the sup-
ply side. The inductor should be as close to the pin as possible.
RF input. An external series capacitor is required as a DC block. The
input match can be improved to <2:1 by using a series capacitor and
shunt inductor.
VCC1
RF IN
From Bias
GND1
Stages
Ground for first stage. For best performance, keep traces physically
short and connect immediately to ground plane. This ground should be
isolated from the backside ground contact.
See pin 4.
5
6
GND1
VPD1
Power Down control for first and second stages. When this pin is “low”,
all first and second stage circuits are shut off. When this pin is 2.8V, all
first and second stage circuits operate normally. V
requires a regu-
PD1
lated 2.8V for the amplifier to operate properly over all specified tem-
perature and voltage ranges. A dropping resistor from a higher
regulated voltage may be used to provide the required 2.8V.
V
adjusts the bias to the 2nd and 3rd stages. For full power oper-
7
8
VMODE
VPD2
MODE
ation, MODE is set low. When operating in a lower output power mode
(<+25dBm) this pin is set high to reduce bias current by up to 50%. An
external series resistor is optional to limit the amount of current
ο
required. At low temperature (-30 C), it is recommended to set V
low to maintain correct operation.
MODE
Power Down control for third stage. When this pin is “low”, all and third
stage circuits are shut off. When this pin is 2.8V, all and third stage cir-
cuits operate normally. V requires a regulated 2.8V for the amplifier
PD
to operate properly over all specified temperature and voltage ranges.
A dropping resistor from a higher regulated voltage may be used to pro-
vide the required 2.8V. A 15pF high frequency bypass capacitor is rec-
ommended.
For best performance, keep traces physically short and connect imme-
diately to ground plane. This ground should be isolated from the back-
side ground contact.
9
GND
RF output and power supply for final stage. This is the unmatched col-
lector output of the third stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1920MHz to 1980MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass-
ing is required for stability.
RF OUT
10
RF OUT
From Bias
Stages
Same as pin 10.
Same as pin 10.
See pin 10.
See pin 10.
11
12
13
RF OUT
RF OUT
2FO
Second harmonic trap. Keep traces physically short and connect imme-
diately to ground plane. This ground should be isolated from backside
ground contact.
Supply for bias reference and control circuits. High frequency bypass-
ing may be necessary.
14
VCC
Same as Pin 1.
Same as Pin 1.
15
16
VCC2
VCC2
Rev A3 010514
2-199
RFMD [ RF MICRO DEVICES ]
