RF2153
Pin
1
Function Description
Interface Schematic
Power supply for second stage and interstage match. Pins 1, 15 and 16
should be connected by a common trace where the pins contact the
printed circuit board.
VCC2
GND2
VCC1
RF IN
Ground for second stage. Keep traces physically short and connect
immediately to ground plane for best performance. This ground should
be isolated from the backside ground contact on top metal layer.
2
3
4
Power supply for first stage and interstage match. V should be fed
See pin 4.
CC
2
through a 1.5nH inductor terminated with a 15pF capacitor on the sup-
ply side.
RF input. An external 15pF series capacitor is required as a DC block
and also provides for an input VSWR of <2:1 typical.
VCC1
RF IN
From Bias
Network
GND1
Ground for first stage. Keep traces physically short and connect imme- See pin 4.
diately to ground plane for best performance. This ground should be
isolated from the backside ground contact on top metal layer.
5
6
GND1
VPD1
Power Down control for first and second stages. When this pin is “low”,
all first and second stage circuits are shut off. When this pin is 2.8V, all
first stage circuits are operating normally. V
requires a regulated
PD1
2.8V for the amplifier to operate properly over all specified temperature
and voltage ranges. A dropping resistor from a higher regulated voltage
may be used to provide the required 2.8V.
For full power operation, MODE is set low. VMODE will reduce the bias
current by up to 50% when set HIGH. Large Signal Gain is reduced
7
8
VMODE
VPD2
approximately 1.5dB at 29dBm P
and Small Signal Gain is reduced
OUT
approximately 6dB. An external series resistor is optional to limit the
amount of current required by the V pin.
MODE
Power Down control for the third stage. When this pin is “low”, the third
stage circuit is shut off. When this pin is 2.8V, the third stage circuit is
operating normally. V requires a regulated 2.8V for the amplifier to
PD
operate properly over all specified temperature and voltage ranges. A
dropping resistor from a higher regulated voltage may be used to pro-
vide the required 2.8V. A 15pF high frequency bypass capacitor is rec-
ommended.
Requires a 15nH inductor.
9
10
BIAS GND
RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the third stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1850MHz to 1910MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass-
ing is required for stability.
RF OUT
From Bias
Network
Same as pin 12.
Same as pin 12.
See pin 10.
See pin 10.
11
12
13
RF OUT
RF OUT
2FO
Second harmonic trap. Keep traces physically short and connect imme-
diately to ground plane. This ground should be isolated from backside
ground contact.
Supply for bias reference and control circuits. High frequency bypass-
ing may be necessary.
14
VCC
Same as pin 1.
Same as pin 1.
15
16
Pkg
Base
VCC2
VCC2
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
2-170
Rev A18 001114
RFMD [ RF MICRO DEVICES ]
