RF2053
lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit
data word representing the register content is presented to the receiver.
Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address is read correctly.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
ENBL Pin
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the PLL to lock.
ENBL Pin
Low
REFSTBY Bit
XO and Bias Block
Analogue Block
Digital Block
0
1
0
1
Off
On
On
On
Off
Off
On
On
On
On
On
On
Low
High
High
Every time the frequency of the synthesizer is re-programmed, ENBL has to be taken high to initiate PLL locking.
RESETB Pin
The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The
device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to
the positive supply.
MODE Pin
The MODE pin controls which PLL programming register bank is active.
For normal operation of the RF2053 the MODE pin should be set high to select the default PLL2 programming registers. It is
possible to set the FULLD bit in the CFG1 register high. This allows the MODE pin to select either PLL1 register bank
(MODE=low) or PLL2 register bank (MODE=high). This may be useful for some applications where two LO frequencies can be
programmed into the registers then the MODE pin used to toggle between them. The ENBL pin will also need to be cycled to re-
lock the synthesizer for each frequency.
ENBL
t1
MODE
t2
Parameter
Description
MODE setup time
MODE hold time
Time
>5ns
>5ns
t1
t2
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