RF2053
Detailed Description
The RF2053 is a wideband RF frequency converter chip which includes a fractional-N phase-locked loop, a crystal oscillator cir-
cuit, an LO buffer, and an RF mixer. The PLL operates with an external VCO. Synthesizer programming, device configuration and
control are achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a sim-
ple three-wire serial interface.
VCO
The RF2053 has been designed for use with an external VCO. The VCO inputs on pins 2 and 3 are differential.
In order to route the VCO input through buffers to the PLL divide circuits then CFG1:EXT_VCO must be set high and the VCO
control word must be set to VCO3, PLL2x0:P2_VCOSEL=10.
The course tuning calibration (CT_CAL) which is not used by the RF2053 should be disabled in order to minimize the PLL lock
time. The VCO signal can be divided by 1, 2, or 4 in the LO divider circuit. The LO divide ratio is set by the PLL2x0:P2_LODIV
control words.
For applications where the required LO frequency is above 2GHz it is recommended that the LO buffer current be increased by
setting CFG5:LO2_I to 1100 (hex value C).
Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the external VCO. The PLL is intended
to use a reference frequency signal of 10MHz to 104MHz. A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz. The reference divider bypass is
controlled by bit CLK_DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remain-
ing three bits CLK_DIV<15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is
enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RF2053 the default programming bank is PLL2, selected by setting the MODE pin high.
The PLL will lock the VCO to the frequency FVCO according to:
FVCO=NEFF*FOSC/R
where NEFF is the programmed fractional N divider value, FOSC is the reference input frequency, and R is the programmed R
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, NEFF
:
NEFF=FVCO*R/FOSC
N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224=16777216.
Example: VCO operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
N
EFF=FVCO *R / FOSC=2220 *1 / 23.92=92.80936454895.
The N value is set to 92, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied
by 224
:
NUM=0.80936454895 * 224 =13,578,884.
Converting N and NUM into binary results in the following:
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