RF3928B
Device Handling/Environmental Conditions
GaN HEMT devices are ESD sensitive materials. Please use proper ESD precautions when handling devices or
evaluation boards.
GaN HEMT Capacitances
The physical structure of the GaN HEMT results in three terminal capacitors similar to other FET technologies.
These capacitances exist across all three terminals of the device. The physical manufactured characteristics of
the device determine the value of the CDS (drain to source), CGS (gate to source) and CGD (gate to drain). These
capacitances change value as the terminal voltages are varied. RFMD presents the three terminal capacitances
measured with the gate pinched off (VGS = -8V) and zero volts applied to the drain. During the measurement pro-
cess, the parasitic capacitances of the package that holds the amplifier is removed through a calibration step.
Any internal matching is included in the terminal capacitance measurements. The capacitance values presented
in the typical characteristics table of the device represent the measured input (CISS), output (COSS), and reverse
(CRSS) capacitance at the stated bias voltages. The relationship to three terminal capacitances is as follows:
CISS = CGD + CGS
COSS = CGD + CDS
CRSS = CGD
DC Bias
The GaN HEMT device is a depletion mode high electron mobility transistor (HEMT). At zero volts VGS the drain of
the device is saturated and uncontrolled drain current will destroy the transistor. The gate voltage must be taken
to a potential lower than the source voltage to pinch off the device prior to applying the drain voltage, taking care
not to exceed the gate voltage maximum limits. RFMD recommends applying VGS = -5V before applying any VDS
.
RF Power transistor performance capabilities are determined by the applied quiescent drain current. This drain
current can be adjusted to trade off power, linearity, and efficiency characteristics of the device. The recom-
mended quiescent drain current (IDQ) shown in the RF typical performance table is chosen to best represent the
operational characteristics for this device, considering manufacturing variations and expected performance.
The user may choose alternate conditions for biasing this device based on performance trade off.
Mounting and Thermal Considerations
The thermal resistance provided as RTH (junction to case) represents only the packaged device thermal charac-
teristics. This is measured using IR microscopy capturing the device under test temperature at the hottest spot of
the die. At the same time, the package temperature is measured using a thermocouple touching the backside of
the die embedded in the device heatsink but sized to prevent the measurement system from impacting the
results. Knowing the dissipated power at the time of the measurement, the thermal resistance is calculated.
In order to achieve the advertised MTTF, proper heat removal must be considered to maintain the junction at or
below the maximum of 200°C. Proper thermal design includes consideration of ambient temperature and the
thermal resistance from ambient to the back of the package including heatsinking systems and air flow mecha-
nisms. Incorporating the dissipated DC power, it is possible to calculate the junction temperature of the device.
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