3.3 Module Interface
Pin
1
Name
GND
I/O
-
Description
Power supply and signal ground. Connect to the host circuit board ground.
Diagnostic serial port output.
2
DIAG_TX
DIAG_RX
GPIO0
O
I
Diagnostic serial port input.
3
Configurable digital I/O port 0. An internal weak pull-up is provided when configured as an input.
Serial data output from the radio.
4
I/O
O
I
5
RADIO_TXD
RADIO_RXD
Serial data input to the radio.
6
UART/SPI flow control output. The module sets this line low when it is ready to accept data from the
host on the RADIO_RXD or MOSI input. When the line goes high, the host must stop sending data.
7
8
9
/HOST_CTS
/HOST_RTS
PWM0
O
I
UART flow control input. The host sets this line low to allow data to flow from the module on the
RADIO_TXD pin. When the host sets this line high, the module will stop sending data to the host.
16-bit pulse-width modulated output with internal low-pass filter. Filter is first-order, with a 159 Hz 3 dB
bandwidth, 10K output resistance.
O
Configurable digital I/O port 2. An internal weak pull-up is provided when configured as an input.
Configurable digital I/O port 1. An internal weak pull-up is provided when configured as an input.
Configurable digital I/O port 3. An internal weak pull-up is provided when configured as an input.
Reserved pin. Leave unconnected.
10
11
12
13
14
15
16
17
18
19
20
21
GPIO2
GPIO1
GPIO3
RSVD
VCC
I/O
I/O
I/O
-
Power supply input, +3.0 to +3.63 Vdc.
I
Power supply and signal ground. Connect to the host circuit board ground.
Power supply and signal ground. Connect to the host circuit board ground.
Active low module hardware reset.
GND
-
GND
-
/RESET
ADC0
I
I
10-bit ADC input 0. ADC full scale reading can be referenced to the module’s +1.8 V regulated supply.
10-bit ADC input 1. ADC full scale reading can be referenced to the module’s +1.8 V regulated supply.
This pin is the SPI master mode input.
ADC1
I
SPI_IN
SPI_OUT
I/O
I/O
This pin is the SPI master mode output.
SPI active low slave select. This pin is an output when the module is operating as a master, and an
input when it is operating as a slave.
22
23
24
25
26
27
/SS
I/O
I/O
O
SPI clock signal. This pin is an output when operating as a master, and an input when operating as
a slave.
SCLK
Module’s +3.3 V regulated supply, available to power external sensor circuits. Current drain on this
output should be no greater than 50 mA.
3.3V_OUT
ADC_REF
WAKE_IN
WAKE_OUT
Module’s +1.8 V regulated supply, used for ratiometric ADC readings. Current drain on this output
should be no greater than 10 mA.
O
Active high interrupt input to wake the module from timer sleep. Can be used to wake module on
event, etc.
I
Active high output asserted when module wakes from timer sleep. Can be used to wake an
external device.
O
Connect to the host circuit board ground plane.
Reserved pin. Leave unconnected.
28
29
30
GND
RSVD
GND
-
-
-
Connect to the host circuit board ground plane.
Table 3.3.1
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Page 13 of 101
WSN802G - 03/16/11
RFM [ RF MONOLITHICS, INC ]
