Pin
Name
Description
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%
resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less
than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less
that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.
11
RREF
THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 Kresistor RTH2
between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value
(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak. The
THLD2 resistor value is given by:
12
THLD2
RTH2 = 1.5*V, where RTH2 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-
peak data slicer operation.
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is
increased by increasing the resistor value. Connecting this pin directly to RREF provides zero theshold. The value of the
resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is
0 to 200K, providing a THLD1 range of 0 to 100 mV. The resistor value is given by:
13
THLD1
RTH1 = 1.48*V + 44.6, where RTH1 is in kilohms and the threshold V is in mV and
V ≥ 0
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 100K. The resistor value is given by:
RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for
proper AGC operation. The minimum value recommended is 20K.
RXDCLK is the clock output from the data and clock recovery circuit. RXDCLK is a CMOS output. When the radio’s internal
data and clock recovery circuit is not used, RXDCLK is a steady low value. When the internal data and clock recovery is
used, RXDCLK is low until a packet start symbol is detected at the output of the data slicer. Each bit following the start
symbol is output at RXDATA on the rising edge of a RXDCLK pulse, and is stable for reading on the falling edge of the
RXDCLK pulse. Once RXDCLK is activated by the detection of a start symbol, it remains active until CFG0 Bit 0 is set to 0.
Normally RXDCLK is reset by the host processor as soon as a packet is received.
14
RXCLK
15
16
GND3
VCC2
GND3 is an IC ground pin.
VCC2 is a positive supply voltage pin. Pin 16 must be bypassed with an RF capacitor, and must also be by passed with a 1
µF tantalum or electrolytic capacitor.
In 3G control mode, CFGDAT is a bi-directional CMOS logic pin. When CFG (Pin 19) is set to a logic 1, configuration data
can be clocked into or out of the radio’s configuration registers through CFGDAT using CFGCLK (Pin 18). Data clocked
into CFGDAT is transferred to a control register each time a group of 8 bits is received (see Figure 4). Pulses on CFGCLK
are used to clock configuration data into and out of the radio through CFGDAT (Pin 17). When writing through CFGDAT, a
data bit is clocked into the radio on the rising edge of a CFGCLK pulse. When reading through CFGDAT, data is output on
the rising edge of the CFGCLK pulse and is stable for reading on the falling edge of the CFGCLK. CFGCLK is inactive
when the CFG (Pin 19) is set at a logic 0. See Page 6 for details of 2G default control mode operation of this pin.
17
18
CFGDAT
CFGCLK
In 3G control mode, pulses on CFGCLK are used to clock configuration data into and out of the radio through CFGDAT
(Pin 17). When writing through CFGDAT, a data bit is clocked into the radio on the rising edge of a CFGCLK pulse. When
reading through CFGDAT, data is output on the rising edge of the CFGCLK pulse and is stable for reading on the falling
edge of the CFGCLK. CFGCLK is inactive when the CFG (Pin 19) is set to logic 0. See Page 6 for details of 2G default
control mode operation of this pin. eac
CFG controls the operation of the CFGDAT (Pin 17) and CFGCLK (Pin 18) pins. If CFG is held at logic 0 when the radio is
powered on, radio operation defaults to 2G control mode as explained on Page 6. Radio operation is switched to 3G serial
control mode the first time CFG is set to logic 1. CFG must be set to a logic 1 before data can be clocked into or out of
CFGDAT by CFGCLK. CFGDAT is inactive when the CFG (Pin 19) is set to logic 0. Setting CFG to a logic 1 will also switch
the radio from sleep mode to active mode.
19
20
CFG
RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an imped-
ance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a
shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some
impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection.
RFIO
RF Monolithics, Inc.
RFM Europe
Phone: (972) 233-2903
Phone: 44 1963 251383
Fax: (972) 387-8148
Fax: 44 1963 251510
E-mail: info@rfm.com
http://www.rfm.com
TR8000-08172007
Page 10 of 14
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RFM [ RF MONOLITHICS, INC ]
