RX62N Group, RX621 Group
1. Overview
Table 1.1
Outline of Specifications (3 / 4)
Classification
Module/Function
Description
Timers
Programmable pulse
generator
· (4 bits x 4 groups) x 2 units
· Pulse output with the MTU output as a trigger
· Maximum of 32-bit pulse output possible
8-bit timers
· (8 bits x 2 channels) x 2 units
· Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
· Capable of output of pulse trains with desired duty cycles or of PWM signals
· The 2 channels of each unit can be cascaded to create a 16-bit timer
· Generation of triggers for A/D converter conversion
· Capable of generating baud-rate clocks for SCI5 and SCI6
Compare match
timer
· (16 bits x 2 channels) x 2 units
· Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer
· 8 bits x 1 channel
· Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
· Switchable between watchdog timer mode and interval timer mode
Independent
watchdog timer
· 14 bits x 1 channel
· Counter-input clock: Dedicated on-chip oscillator
Realtime clock
· Clock source: Subclock
· Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Communication
function
Ethernet controller
· Input and output of Ethernet/IEEE 802.3 frames
· Transfer at 10 or 100 Mbps
· Full- and half-duplex modes
· MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
· Detection of Magic PacketsTM* or output of a "wake-on-LAN" signal (WOL)
· Compliance with flow control as defined in IEEE 802.3x standards
Note: * Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
DMA controller for
Ethernet controller
· Alleviation of CPU loads by the descriptor control method
· Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
USB 2.0 host/
function module
· Includes a UDC (USB Device Controller) and transceiver for USB 2.0
· Single port (176-pin products: two ports)
· Compliance with the USB 2.0 specification
· Transfer rate: Full speed (12 Mbps)
· Self-power mode and bus power are selectable
· OTG (On the Go) operation is possible
· Incorporates 2 Kbytes of RAM as a transfer buffer
Serial
communications
interfaces
· 6 channels
· Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
· Multi-processor communications function
· On-chip baud rate generator allows selection of the desired bit rate
· Choice of LSB-first or MSB-first transfer
· Average transfer rate clock can be input from TMR timers for SCI5 and SCI6
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 4 of 146
RENESAS [ RENESAS TECHNOLOGY CORP ]
