R2S15902FP
Relationship Between Data and Clock
Data signal is read at the rising edge of CLOCK.
Make "H" at the timing which
DATA of D0-D23 make latch.
DATA
D0
D1
D2
D3
D21
D22
D23
CLOCK
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
When CLOCK is "L" and latch signal is created,
latch signal is read at the falling edge of DATA.
Clock and Data Timings
DATA
(D0
to
D23)
t
cr
LATCH
75%
25%
tSLD
tSLD
tHLD tSHD
tHHD
tHLD
tSC
75%
50%
25%
CLOCK
tr
tWHC
tf
tWLC
Timing Definition of Digital Block
Parameter
CLOCK cycle time
CLOCK pulse width ("H" level)
CLOCK pulse width ("L" level)
Rising time of clock and data
Falling time of clock and data
DATA setup time (Rising time of clock)
DATA setup time (Falling time of clock)
DATA hold time ("H" level)
DATA hold time ("L" level)
CLOCK setup time
Symbol
tcr
tWHC
tWLC
tr
tf
tSHD
tSLD
tHHD
tHLD
tSC
Min
8
3.2
3.2
⎯
⎯
1.6
1.6
1.6
1.6
1.6
Limits
Typ
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max
⎯
⎯
⎯
0.8
0.8
⎯
⎯
⎯
⎯
⎯
µs
Unit
Rev.1.0 Nov 22, 2005 page 5 of 15
RENESAS [ RENESAS TECHNOLOGY CORP ]
