R1LP0408C-I Series
Low VCC Data Retention Characteristics
(Ta = −40 to +85°C)
Parameter
Symbol Min Typ Max Unit Test conditions*3
VCC for data retention
VDR
2
10
8
V
CS# ≥ VCC − 0.2 V, Vin ≥ 0 V
Data
−5SI
to +85°C
to +70°C
to +40°C
to +25°C
to +85°C
to +70°C
to +40°C
to +25°C
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
tCDR
µA VCC = 3.0 V, Vin ≥ 0 V
retention
current
µA CS# ≥ VCC − 0.2 V
1.0*2
0.8*1
3
µA
µA
µA
µA
µA
µA
3
−7LI
0
20
16
1.0*2 10
0.8*1 10
Chip deselect to data retention time
Operation recovery time
ns
ns
See retention waveform
tR
t
RC*4
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS# Controlled)
tR
tCDR
Data retention mode
VCC
4.5 V
2.2 V
VDR
CS#
0 V
CS# ≥ VCC – 0.2 V
Rev.2.00, May.26.2004, page 12 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
