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R1LP0408CSB-7LC 参数 Datasheet PDF下载

R1LP0408CSB-7LC图片预览
型号: R1LP0408CSB-7LC
PDF下载: 下载PDF文件 查看货源
内容描述: 4M SRAM( 512千字】 8位)的 [4M SRAM (512-kword 】 8-bit)]
分类和应用: 静态存储器
文件页数/大小: 14 页 / 93 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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R1LP0408C-C Series  
Write Cycle  
R1LP0408C-C  
-5SC  
-7LC  
Min  
70  
60  
0
Parameter  
Symbol  
tWC  
Min  
55  
50  
0
Max  
20  
20  
Max  
25  
25  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Notes  
Write cycle time  
Chip selection to end of write  
Address setup time  
tCW  
4
5
tAS  
Address valid to end of write  
Write pulse width  
tAW  
50  
40  
0
60  
50  
0
tWP  
3, 12  
6
Write recovery time  
tWR  
Write to output in high-Z  
Data to write time overlap  
Data hold from write time  
Output active from end of write  
Output disable to output in high-Z  
tWHZ  
tDW  
0
0
1, 2, 7  
25  
0
30  
0
tDH  
tOW  
5
5
2
tOHZ  
0
0
1, 2, 7  
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions  
and are not referred to output voltage levels.  
2. This parameter is sampled and not 100% tested.  
3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later  
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going  
high or WE# going high. tWP is measured from the beginning of write to the end of write.  
4. tCW is measured from CS# going low to the end of write.  
5. tAS is measured from the address valid to the beginning of write.  
6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.  
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase  
to the outputs must not be applied.  
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#  
transition, the output remain in a high impedance state.  
9. Dout is the same phase of the write data of this write cycle.  
10. Dout is the read data of next address.  
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of  
the opposite phase to the outputs must not be applied to them.  
12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of  
data bus contention. tWP tDW min + tWHZ max  
Rev.2.00, May.26.2004, page 8 of 12