M66311P/FP
Functional Description
As M66311P/FP uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED
drive while maintaining low power consumption and allowance for high noises.
Each bit of a shiftregister consists of two flip–flops having independent clocks for shifting and latching.
As for clock input, shift clock input CK
S
and latch clock input CK
L
are independent from each other, shift and latch
operations being made when “L” changes to “H”.
Serial data input A is the data input of the first–step shiftregister and the signal of A shifts shifting registers one by one
when a pulse is impressed to CK
S
. When A is “H”, the signal of “L” shifts.
When the pulse is impressed to CK
L
, the contents of the shifting register at that time are stored in a latching register,
and they appear in the outputs from
Q
A
to
Q
P
.
Outputs from
Q
A
to
Q
P
are open drain outputs.
To extend the number of bits, use the serial data output SQ
P
which shows the output of the shifting register of the 16th
bit.
If CK
S
and CK
L
are connected, the state of the shifting register with one clock delay is outputted to
Q
A
to
Q
P
.
When reset input
R
is changed to “L”,
Q
A
to
Q
P
and SQ
P
are reset. In this case, shifting and latching registers are set.
If “H” is impressed to output enable input OE,
Q
A
to
Q
P
reaches the high impedance state, but SQ
P
does not reach the
high impedance state. Furthermore, change in OE does not affect shift operation.
Function Table
(Note)
Input
Operation Mode
Reset
Shift
latch
Shift t1
Latch t2
Latch t2
Output disable
R
L
H
H
H
H
X
CK
S
CK
L
X
↑
X
↑
X
X
X
X
↑
X
↑
X
A
X
H
X
L
X
X
OE
X
L
L
L
L
H
Q
A
Z
Q
A
L
Z
Z
0
Parallel Data Output
Q
B
Z
Q
B
0
Q
C
Z
Q
C
0
Q
D
Z
Q
D
0
Q
E
Z
Q
E
0
Q
F
Z
Q
F
0
Q
G
Z
Q
G
0
Q
H
Z
Q
H
0
Q
I
Z
Q
I
0
q
H0
Q
I
0
q
H0
Z
Q
J
Z
Q
J
0
Q
K
Z
Q
K
0
Q
L
Z
Q
L
0
Q
M
Z
Q
M
0
Q
N
Z
Q
N
0
Q
O
Z
Q
O
0
Q
P
Z
Q
P
0
Serial
Data
Output
SQ
P
Remarks
L
q
O
0
q
A0
q
A0
Z
q
B0
q
B0
Z
q
C0
q
C0
Z
q
D0
q
D0
Z
q
E0
q
E0
Z
q
F0
q
F0
Z
q
G0
q
G0
Z
q
I0
q
I0
Z
q
J0
q
J0
Z
q
K0
q
K0
Z
q
L0
q
L0
Z
q
M0
q
M0
Z
q
N0
q
N0
Z
q
O0
q
O0
Z
q
O0
q
O0
q
P
operation Shift t1
Q
A
0
Q
B
0
Q
C
0
Q
D
0
Q
E
0
Q
F
0
Q
G
0
Q
H
0
Q
J
0
Q
K
0
Q
L
0
Q
M
0
Q
N
0
Q
O
0
Q
P
0
q
O0
–
Output
lighting
"H"
Output
lights-out
"L"
–
Note
↑:
Change from low-level to high-level
Q
0
: Output state
Q
before CK
L
changed
X: Irrelevant
q
0
: Contents of shift register before CK
S
changed
q: Contents of shift register
t
1
, t
2
: t
2
is set after t
1
is set
Z: High impedance
REJ03F0177-0201 Rev.2.01 Mar 31, 2008
Page 3 of 9
RENESAS [ RENESAS TECHNOLOGY CORP ]
