M66312P/FP
Functional Description
As M66312 uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive
while maintaining low power consumption and allowance for high noises.
Each bit of a shiftregister consists of two flip-flops having independent clocks for shifting and latching.
As for clock input, shift clock input CK
S
and latch clock input CK
L
are independent from each other, shift and latch
operations being made when “L” changes to “H”.
Serial data input A is the data input of the first-step shiftregister and the signal of A shifts shiting registers one by one
when a pulse is impressed to CK
S
. When A is “H”, the signal of “H” shifts. When A is “L”, the signal of “L” shifts.
When the pulse is impressed to CK
L
, the contents of the shifting register at that time are stored in a latching register,
and they appear in the output from Q
A
through Q
H
are 3-state outputs.
To extend the number of bits, serial data output SQ
H
is used to output the 8-bit of the shift register.
By connecting CK
S
and CK
L
, the shift register state delayed by 1 clock cycle is output at Q
A
through Q
H
.
When reset input
R
is low, shift register and SQ
H
will be reset. To reset Q
A
through Q
H
to low-level, CK
L
must be
changed from low-level to high-level after the shift register is reset by
R.
When output-enable input
OE
is high, Q
A
through Q
H
will become high impedance state, but SQ
H
is not changed.
Even if
OE
is changed, shift operation is not affected.
Function Table
(Note)
Input
Operation Mode
Reset
Shift
latch
Shift t1
Latch t2
Shift t1
Latch t2
Latch t2
3 state
R
L
X
H
H
H
H
X
CK
S
X
X
↑
X
↑
X
X
CK
L
X
↑
X
↑
X
↑
X
A
X
X
H
X
L
X
X
OE
L
L
L
L
L
L
H
Q
A
Q
A0
L
Q
A
H
Q
A0
L
Z
0
Parallel Data Output
Q
B
Q
B0
L
Q
B
0
Q
C
Q
C0
L
Q
C
0
Q
D
Q
D0
L
Q
D
0
Q
E
Q
E0
L
Q
E
0
Q
F
Q
F0
L
Q
F0
q
E0
Q
F0
q
E0
Z
Q
G
Q
G0
L
Q
G
0
Q
H
Q
H0
L
Q
H
0
Serial Data
Output SQ
H
L
L
q
G0
q
G0
q
G0
q
G0
q
H
q
A0
Q
B0
q
A
Z
0
q
B0
Q
C0
q
B
Z
0
q
C0
Q
D0
q
C
Z
0
q
D0
Q
E0
q
D
Z
0
q
F0
Q
G0
q
F0
Z
q
G0
Q
H0
q
G
Z
0
operation Shift t1
Note
↑:
Change from low-level to high-level
0
Q : Output state Q before CK
L
changed
X: Irrelevant
0
q : Contents of shift register before CK
S
changed
q: Contents of shift register
t
1
, t
2
: t
2
is set after t
1
is set
Z: High impedance
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 3 of 8
RENESAS [ RENESAS TECHNOLOGY CORP ]
