V
CC
M65761FP
13
26
68
RESET
62
CS
64
A0
39
50
75
81
87
93
100
59
69
Block Diagram
PD0
2
PD10
12
PD11
15
67
A3
63
BHE
58
WR
57
RD
71
D0
74
D3
77
D4
Host bus I/F
PD21
25
Switch
Line memory
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 2 of 33
Context table RAM
Context generation
QM-coder
Table RAM probability estimation
Typical prediction
PD22
28
PD31
37
PD0 to 11 = CX0 to 11
PD15 =
PEUPE
PDRQ
38
PDAK
43
PDRD
41
80
D7
83
D8
86
D11
PDWR
42
Image data context I/F
PRDY
45
Pixel data
(=
XRDY)
PTIM
47
89
D12
92
D15
(=
XTIM)
Context data
PXCK
48
54
DMARQ
56
DMAAK
53
INTR
55
BUS16
61
MCLK
98
TEST1
99
TEST0
1
14 27 40 51 60 70 76 82 88 94
GND
PXCKO
95
SVID
46
(=
SPIX)
RVID
44
(=
RPIX)
XCLK
52
XWAIT
49
96 97
Leave TOUT
1
and TOUT
2
open.
TOUT
1
,
2
RENESAS [ RENESAS TECHNOLOGY CORP ]
