M65667FP
Block Diagram
SCK
CSYNC (s)
/TEST1
BGP (s)
/TEST0
Yin
Sync tip
clamp
Cin
Vdd/Vss
For test
DATA
CLK
ACK
Vin (s)
15
3
3
I
2
C
I/F
A/D
8 bit
RAM (1H)
V-chip
data slicer
Luma
clamp
Delay
Y
6
Back porch
clamp
AFC
Timing gen
(Decode)
B-Y
Demod
Tint
R-Y
6
6
Y
B-Y
R-Y
Timing gen
(Memory
cont)
Vert-filter
&
MUX
Bias
Y-PlP
Bias
C-PlP
C-PlPin
Y
Y/C SEP
(LPF, BPF)
Sync tip
clamp
2
HD
(I
2
C)
Y-PlPin
Vrt (m)
Vrb (m)
Sync
sep
Phase
select
HPLL
4 fsc
Delay
C
SWMG
/TEST7
ADJ-Ysub
Yout-sub
D/A
8 bit
D/A
8 bit
Demux
Delay
MIX
Delay
LPF
&MPY
6
Y
RAM
96 Kbits
Encode
6 B-Y
6 R-Y
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
Cout-sub
fsc
Level
detect
ADJ-Csub
Vin (m)
Bias
A/D
8 bit
Burst data
sampling
Phase
detect
Lock/Free-run
via I
2
C
VCXO
driver
BIAS
4 fsc
VCXO in
VCXO
VCXO out
Vrt (m)
Vrb (m)
2
RESET
MCK
BGP (m)
/TEST2
fsc
/TEST3
SWM
/TEST4
REJ03F0185-0201 Rev.2.01 Mar 31, 2008
Page 2 of 12
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