M62384FP
(2) Address data
D8
0
0
1
1
D9
0
1
0
1
Channel Selection
AO1 selected
AO2 selected
AO3 selected
AO4 selected
DAC Data
D7
0
0
0
0
D6
0
0
0
0
D5
0
0
0
0
D4
0
0
0
0
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
1
1
D0
0
1
0
1
D-A output
(0/256)×Vref
(1/256)×Vref
(2/256)×Vref
(3/256)×Vref
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
(254/256)×Vref
(255/256)×Vref
Data Timing Chart
SDI
D11
D10
D9
D8
D2
D1
D0
SCK
SLD
Ao
When SLD is high, data captured in the shift register is loaded into the 8-bit latch
corresponding to the address. Therefore, SCK should be held high or low when
SLD is high.
Rev.1.0, Sep.19.2003, page 6 of 8