M62352AGP
Digital Data Format
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
First
MSB
D11
DAC data
DAC select data
DAC Data
D0
0
1
0
1
:
0
1
D1
0
0
1
1
:
1
1
D2
0
0
0
0
:
1
1
D3
0
0
0
0
:
1
1
D4
0
0
0
0
:
1
1
D5
0
0
0
0
:
1
1
D6
0
0
0
1
:
1
1
D7
0
0
0
0
:
1
1
D/A Output
(VrefU – VrefL) / 256
×
1 + VrefL [V]
(VrefU – VrefL) / 256
×
2 + VrefL [V]
(VrefU – VrefL) / 256
×
3 + VrefL [V]
(VrefU – VrefL) / 256
×
4 + VrefL [V]
:
(VrefU – VrefL) / 256
×
255 + VrefL [V]
VrefU [V]
(1 LSB)
(2 LSB)
(3 LSB)
(4 LSB)
(255 LSB)
(256 LSB)
Note: VrefU = V
DD
, VrefL = V
SS
DAC Select Data
D8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC Selection
Don’t care
AO1 select
AO2 select
AO3 select
AO4 select
AO5 select
AO6 select
AO7 select
AO8 select
AO9 select
AO10 select
AO11 select
AO12 select
Don’t care
Don’t care
Don’t care
Timing Chart (Model)
CLK
SI
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LD
AO1
to
AO12
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 6 of 8
RENESAS [ RENESAS TECHNOLOGY CORP ]
