M62320P/FP
•
In case the I/O setting is different between each terminals.
An example: the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals,
respectively.
Start
condition
Stop
condition
Slave address
I/O setting
DATA
DATA
SDA
SCL
D0
to
D3
D4
to
D7
0
1
1
1
A2 A1 A0
0
A
P7 P6 P5 P4 P3 P2 P1 P0
A
D17 D16 D15 D14 D13 D12 D11 D10
A
D27 D26 D25 D24 D23 D22 D21 D20
A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Data output
Hi-Z
D
1X
Data output
D
2X
Hi-Z
Start
condition
Slave address
DATA
DATA
DATA
Stop
condition
SDA
SCL
0
1
1
1
A2 A1 A0
1
A
D17 D16 D15 D14 D13 D12 D11 D10
A
D37 D36 D35 D34 D33 D32 D31 D30
A
D47 D46 D45 D44 D43 D42 D41 D40
A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
D0 to D3
D4 to D7
(instance)
D4 to D7
output
D
1X
D
2X
D
3X
D
4X
Data latch
Hi-Z
Data latch
Data latch
•
Write mode
The terminal assigned as an output provides the data written in the output data latch.
After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are output after
the I/O setting has been done. Finally the assigned output are provided after the 8-bit data transmission.
The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data setting.
•
Read mode
The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the terminal
assigned as an input, and then the latched data is output via the SDA line.
The data of the output assigned terminal is also handled in the same procedures as above.
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 8 of 10
RENESAS [ RENESAS TECHNOLOGY CORP ]
