M61303FP
I2C BUS Control Section SDA, SCL Characteristics
Item
Min. input LOW voltage
Symbol
VIL
Min.
−0.5
3.0
0
Max.
1.5
5.5
100
⎯
Unit
V
Max. input HIGH voltage
VIH
V
SCL clock frequency
fSCL
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated
The LOW period of the clock
tBUF
4.7
4.0
4.7
4.0
4.7
0
tHD:STA
tLOW
⎯
⎯
The HIGH period of the clock
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
⎯
Set up time for start condition (Only relevant for a repeated start condition)
Hold time DATA
⎯
⎯
Set-up time DATA
250
⎯
⎯
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
Set-up time for stop condition
1000
300
⎯
tf
⎯
tSU:STO
4.0
tr, tf
tBUF
VIL
SDA
VIH
tHD: STA
tSU: DAT
tHD: DAT
tSU: STA
tSU: STO
VIL
VIH
SCL
tLOW
tHIGH
S
S
P
S
Rev.2.00 Sep 14, 2006 page 6 of 24
RENESAS [ RENESAS TECHNOLOGY CORP ]
