M5295AL/AP/AFP
Operating Description
V
TH2(H)
V
TH1
V
TH2(L)
V
TH1
V
CC
0V
V
TH3(H)
TC
V
TH3(L)
0V
V
IN
0V
RST1
0V
RST2
0V
t
RST(1)
t
WD
t
RST(2)
(1) (2)(3)
(4) (5)
(6)
(7) (8)
(9)(10)(11)
(1): The V
CC
rises up to 0.8 V, then
RST1
and
RST2
generates low output, and rising up to 4.25 V,
charge of C1 begins.
(2): The V
CC
rises up to 4.7 V, then
RST2
generates high.
(3), (4): The voltage at TC pin is 2 V, then
RST2
generates high, when 4 V, C1 is discharged and
RST1
generates low.
(5): The voltage at TC pin falls to 2 V, then
RST1
generates high unless normal clock signal is entered
to WD pin,
RST1
repeats this operation.
(6), (7): Before the voltage at TC pin reaches 4 V, if normal clock signal is entered to WD pin, low
RST1
is
canceled.
(8), (9): In the case of entrance of abnormal signal input, as the waveform of TC pin repeats charge and
discharge of
RST1
alternatively from 2 V to 4 V, the
RST1
repeats high and low output operation.
(10): The V
CC
falls to 4.6 V, then
RST2
generates low, this detective voltage has a 100 mV hysteresis.
(11): When V
CC
goes down to 4.25 V(V
TH1
), the status of TC pin is switched to discharge. When the
potentional at TC pin is detected being V
TH3(H)
or V
TH3(L)
, the status of
RST1
becomes "low".
Terminology
t
RST(1)
: Time required for TC pin potential to rise from 0 V V
TH3(L)
when V
CC
is being applied.
t
WD
: Time required for TC pin potential to rise from V
TH3(L)
to V
TH3(H)
.
t
RST(2)
: Time required for TC pin potential to go down from V
TH3(H)
to V
TH3(L)
.
Figure 1 Operating Waveform
REJ03D0780-0200 Rev.2.00 Jun 15, 2007
Page 4 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
