M52749FP
I
2
C BUS Control Section SDA, SCL Characteristics
Item
Min. input LOW voltage
Max. input HIGH voltage
SCL clock frequency
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated
The LOW period of the clock
The HIGH period of the clock
Set up time for start condition (Only relevant for a repeated start condition)
Hold time DATA
Set-up time DATA
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
Set-up time for stop condition
Symbol
V
IL
V
IH
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
tr
tf
t
SU:STO
Min.
−0.5
3.0
0
1.3
0.6
1.3
0.6
0.6
0.1
100
0.6
Max.
1.5
5.5
400
300
300
Unit
V
V
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Timing Chart
tr, tf
V
IL
SDA
V
IH
t
BUF
t
HD: STA
V
IL
SCL
V
IH
t
SU: DAT
t
HD: DAT
t
SU: STA
t
SU: STO
t
LOW
S
t
HIGH
S
P
S
REJ03F0194-0201 Rev.2.01 Mar 31, 2008
Page 6 of 26
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