3858 Group
Timer Z2
■16-bit Timer
(2) Event counter mode
■Mode selection
The timer Z2 is a 16-bit timer. When the timer reaches “000016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When the timer underflows, the interrupt request bit
corresponding to the timer Z2 is set to “1”.
This mode can be selected by setting “000” to the timer Z2 operat-
ing mode bits (bits 2 to 0) and setting “1” to the timer/event
counter mode switch bit (bit 7) of the timer Z2 mode register (ad-
dress 002B16).
The valid edge for the count operation depends on the CNTR3 ac-
tive edge switch bit (bit 5) of the timer Z2 mode register (address
002B16). When it is “0”, the rising edge is valid. When it is “1”, the
falling edge is valid.
When reading/writing to the timer Z2, perform reading/writing to
both the high-order byte and the low-order byte. When reading the
timer Z2, read from the high-order byte first, followed by the low-
order byte. Do not perform the writing to the timer Z2 between
read operation of the high-order byte and read operation of the
low-order byte. When writing to the timer Z2, write to the low-order
byte first, followed by the high-order byte. Do not perform the
reading to the timer Z2 between write operation of the low-order
byte and write operation of the high-order byte.
■Interrupt
The interrupt at an underflow is the same as the timer mode’s.
■Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR3 pin and port P23 to input in
this mode.
The timer Z2 can select the count source by the timer Z2 count
source selection bits of timer Z2 count source selection register
(bits 7 to 4 at address 003016).
Figure 30 shows the timing chart of the timer/event counter mode.
(3) Pulse output mode
■Mode selection
Timer Z2 can select one of seven operating modes by setting the
timer Z2 mode register (address 002B16).
This mode can be selected by setting “001” to the timer Z2 operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (ad-
dress 002B16).
(1) Timer mode
■Mode selection
This mode can be selected by setting “000” to the timer Z2 operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (ad-
dress 002B16).
■Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
■Count source selection
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
■Interrupt
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
The interrupt at an underflow is the same as the timer mode’s.
■Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR3 pin. When the CNTR3 active edge switch bit (bit 5) of
the timer Z2 mode register (address 002B16) is “0”, the output
starts with “H” level. When it is “1”, the output starts with “L” level.
■Precautions
■Interrupt
When an underflow occurs, the timer Z2/CNTR3 interrupt request
bit (bit 5) of the interrupt request register 1 (address 003C16) is set
to “1”.
■Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The double-function port of CNTR3 pin and port P23 is automati-
cally set to the timer pulse output port in this mode.
The output from CNTR3 pin is initialized to the level depending on
CNTR3 active edge switch bit by writing to the timer.
When the value of the CNTR3 active edge switch bit is changed,
the output level of CNTR3 pin is inverted.
The timer count operation is started by setting “0” to the timer Z2
count stop bit (bit 6) of the timer Z2 mode register (address
002B16).
When the timer reaches “000016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
Figure 31 shows the timing chart of the pulse output mode.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
Rev.1.10 Apr 3, 2006 page 35 of 75
REJ03B0139-0110
RENESAS [ RENESAS TECHNOLOGY CORP ]
