MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
Direction registers
The 3802 group has 56 programmable I/O pins arranged in seven
I/O ports (ports P0 to P6). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Pin
P0
0
–P0
7
Name
Port P0
Input/Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
Non-Port Function
Address low-order byte
output
Address high-order
byte output
Related SFRs
CPU mode register
Ref.No.
P1
0
–P1
7
Port P1
CPU mode register
(1)
P2
0
–P2
7
P3
0
/DA
1
P3
1
/DA
2
P3
2
–P3
7
P4
0
/INT
4
,
P4
1
/INT
0
,
P4
3
/INT
2
P4
4
/R
X
D,
P4
5
/T
X
D,
P4
6
/S
CLK1
,
P4
7
/S
RDY1
P5
0
/SIN
2
,
P5
1
/S
OUT2
,
P5
2
/S
CLK2
,
P5
3
/S
RDY2
P5
4
/CNTR
0
,
P5
5
/CNTR
1
P5
6
/PWM
P5
7
/INT
3
P6
0
/AN
0
–
P6
7
/AN
7
Port P2
Data bus I/O
D-A conversion output
Control signal I/O
External interrupt input
CPU mode register
AD/DA control register
CPU mode register
CPU mode register
Interrupt edge selection
register
Serial I/O1 control
Port P3
(2)
(1)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Port P4
Input/output,
individual bits
CMOS 3-state output
CMOS compatible
input level
Serial I/O1 function I/O
register
UART control register
Serial I/O2 function I/O
Port P5
Input/output,
individual bits
CMOS 3-state output
CMOS compatible
input level
Serial I/O2 control
register
Timer X and Timer Y
function I/O
PWM output
External interrupt input
Timer XY mode register
PWM control register
Interrupt edge selection register
(12)
(13)
(3)
(14)
Port P6
Input/output,
individual bits
CMOS 3-state output
CMOS compatible
input level
A-D conversion input
Note 1:
For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-
tion I/O ports, refer to the applicable sections.
2:
Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC
to V
SS
through the input-stage gate.
11
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