MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
When the data slicer function is not used, the data slicer circuit can
DATA SLICER
be cut off by setting bit 0 of data slicer control register 1 (address
00EA16) to “0.” Also, the timing signal generating circuit can be cut
off by setting bit 0 of data slicer control register 2 (address 00EB16)
to “0.” These settings can realize the low-power dissipation.
The M37274EFSP includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a
composite video signal. A composite video signal which makes the
sync chip’s polarity negative is input to the CVIN pin.
0.1 µF
Composite
video
signal
470Ω
1 kΩ
15 kΩ
Sync pulse counter
register
(address 020F16)
560 pF
1 µF
Hundred of kiloohms
200 pF
to 1 MΩ
CVIN
HSYNC
HLF
RVCO
Clock run-in register 2
(address 00E716)
Synchronizing
signal counter
1 0 0 1 1 1
1
Clamping
circuit
Data slicer control register 2
(address 00EB16)
0
0 0
Synchronizing
Low-pass
filter
Sync slice
circuit
separation
circuit
Data slicer control register 1
(address 00EA16)
0
0 0
Timing signal
generating
circuit
Data slicer ON/OFF
Window register
(address 00E216)
0 0
VHOLD
Reference
voltage
generating
circuit
+
–
Clock run-in
determination
circuit
1000 pF
0 1 0 1
Comparator
Clock run-in register 1
(address 00E616)
Data slice line
specification
circuit
Data slicer control
register 3
(address 021016)
1 0 0
Caption position register
(address 00E016)
Start bit detecting
circuit
Clock run-in detect
register 3
(address 020816)
Start bit position register
(address 00E116)
Data clock
generating circuit
Clock run-in
register 3
(address 020916)
Clock run-in detect register 1
(address 00E816)
External circuit
16-bit shift register
Note: Make the length of wiring which is
connected to VHOLD, HLF, RVCO
and CVIN pin as short as possible
so that a leakage current may
not be generated when mounting
a resistor or a capacitor on each
pin.
high-order
low-order
Clock run-in detect register 2
(address 00E916)
Data register 2
(address 00E516)
Data register 1
(address 00E416)
Data slicer
interrupt
request
Interrupt request
generating circuit
Data register 4
(address 00ED16)
Sync slice register 3
(address 00E316)
Data register 3
(address 00EC16)
0 0 0 0 1 0 1
Data bus
Fig. 31. Data Slicer Block Diagram
37
RENESAS [ RENESAS TECHNOLOGY CORP ]
