MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER
(1)A-D Conversion Register (AD)
(3)Comparison Voltage Generator (Resistor
A-D conversion reigister is a read-only register that stores the result
Ladder)
of an A-D conversion. This register should not be read during A-D
conversion.
The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the refer-
ence voltage Vref.
(2)A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 1 and 0 of this
(4)Channel Selector
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and VCC. When
not using the A-D converter, the resistor ladder can be cut off from
the internal VCC by setting this bit to “0,” accordingly providing low-
power dissipation.
The channel selector connects an analog input pin, selected by bits
1 and 0 of the A-D control register, to the comparator.
(5)Comparator and Control Circuit
The conversion result of the analog input voltage and the reference
voltage “Vref” is stored in the A-D conversion register. The A-D con-
version completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.
Data bus
b7
b0
A-D control register
address 00EF16
(
)
2
A-D conversion
interrupt request
A-D control circuit
AD1
AD2
AD3
Compa-
rator
A-D conversion register
8
(address 00EE16
)
AD4
AD5
Switch tree
AD6
Resistor ladder
V
SS VCC
Fig. 27. A-D Comparator Block Diagram
33
RENESAS [ RENESAS TECHNOLOGY CORP ]
