M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Address 00DB16
2
I C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2) [Address 00DB16]
B
Name
Functions
After reset R W
0
SCL frequency control bits
Setup value of
CCR4–CCR0
Standard clock High speed
0
R W
to (CCR0 to CCR4)
4
mode
clock mode
00 to 02
03
Setup disabled Setup disabled
333
250
Setup disabled
Setup disabled
04
05
400 (See note)
166
100
06
83.3
500/CCR value
17.2
1000/CCR value
34.5
1D
1E
1F
16.6
33.3
32.3
16.1
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
0
R W
6
7
ACK bit
(ACK BIT)
0: ACK is returned.
1: ACK is not returned.
0
0
R W
R W
ACK clock bit
(ACK)
0: No ACK clock
1: ACK clock
Note: At 400 kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Address 00DC16
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
0
Serial I/O mode register (SM) [Address 00DC16
]
B
Name Functions
R W
R W
After reset
b1 b0
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
0
0 0: f(XIN)/4
0 1: f(XIN)/16
1 0: f(XIN)/32
1 1: f(XIN)/64
0
0
R W
R W
2
3
0: External clock
1: Internal clock
Synchronous clock
selection bit (SM2)
Serial I/O port
selection bit (SM3)
0: P2
0
, P2
1
1: SCLK,
S
OUT
0
0
R
4
5
Fix this bit to “0.”
W
R W
R W
0: LSB first
1: MSB first
Transfer direction
selection bit (SM5)
Serial input pin
selection bit (SM6)
0: Input signal from SIN pin.
1: Input signal from SOUT pin.
0
0
6
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
—
R
Rev.1.00 Oct 01, 2002 page 99 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
