M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
13. A-D COMPARISON CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
0
Max.
6
—
—
Resolution
bits
Absolute accuracy
±1
±2
LSB
14. D-A CONVERSION CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
1
Max.
6
2
3
4
bits
LSB
µs
—
—
Resolution
Absolute accuracy
Setting time
tsu
Ro
2.5
kΩ
Output resistor
Note: Only M37221EASP/FP have a built-in D-A converter.
2
15. MULTI-MASTER I C-BUS BUS LINE CHARACTERISTICS
Standard clock mode High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
4.0
4.7
Max.
Min.
1.3
Max.
tBUF
Bus free time
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
tHD; STA
tLOW
Hold time for START condition
LOW period of SCL clock
0.6
1.3
tR
Rising time of both SCL and SDA signals
Data hold time
1000
300
20+0.1Cb
0
300
0.9
tHD; DAT
tHIGH
0
HIGH period of SCL clock
4.0
0.6
tF
Falling time of both SCL and SDA signals
Data set-up time
20+0.1Cb
100
300
tSU; DAT
tSU; STA
tSU; STO
250
4.7
4.0
Set-up time for repeated START condition
Set-up time for STOP condition
0.6
0.6
Note: Cb = total capacitance of 1 bus line
SDA
tSU;STO
tHD;STA
tBUF
tLOW
tR
tF
Sr
P
P
S
SCL
S : Start condition
Sr : Restart condition
P : Stop condition
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
2
Fig.15.1 Definition Diagram of Timing on Multi-master I C-BUS
Rev.1.00 Oct 01, 2002 page 81 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
