9.2.4
9.2.5
9.2.6
DMA Destination Address Registers ----------------------------------------------------------------------9-20
DMA Transfer Count Registers -----------------------------------------------------------------------------9-21
DMA Interrupt Related Registers ---------------------------------------------------------------------------9-22
9.3 Functional Description of the DMAC----------------------------------------------------------------------------------9-27
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
DMA Transfer Request Sources----------------------------------------------------------------------------9-27
DMA Transfer Processing Procedure ---------------------------------------------------------------------9-33
Starting DMA ----------------------------------------------------------------------------------------------------9-34
DMA Channel Priority -----------------------------------------------------------------------------------------9-34
Gaining and Releasing Control of the Internal Bus ----------------------------------------------------9-34
Transfer Units ---------------------------------------------------------------------------------------------------9-35
Transfer Counts-------------------------------------------------------------------------------------------------9-35
Address Space--------------------------------------------------------------------------------------------------9-35
Transfer Operation ---------------------------------------------------------------------------------------------9-35
9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------9-37
9.3.11 Each Register Status after Completion of DMA Transfer --------------------------------------------9-37
9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------9-38
CHAPTER 10 MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers ---------------------------------------------------------------------------------------10-2
10.2 Common Units of Multijunction Timers -----------------------------------------------------------------------------10-9
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
MJT Common Unit Register Map--------------------------------------------------------------------------10-10
Prescaler Unit --------------------------------------------------------------------------------------------------10-12
Clock Bus and Input/Output Event Bus Control Unit -------------------------------------------------10-13
Input Processing Control Unit ------------------------------------------------------------------------------10-17
Output Flip-flop Control Unit --------------------------------------------------------------------------------10-26
Interrupt Control Unit -----------------------------------------------------------------------------------------10-35
10.3 TOP (Output-Related 16-Bit Timer) ---------------------------------------------------------------------------------10-64
10.3.1 Outline of TOP --------------------------------------------------------------------------------------------------10-64
10.3.2 Outline of Each Mode of TOP -------------------------------------------------------------------------------10-66
10.3.3 TOP Related Register Map ----------------------------------------------------------------------------------10-68
10.3.4 TOP Control Registers ----------------------------------------------------------------------------------------10-70
10.3.5 TOP Counters (TOP0CT–TOP10CT) ---------------------------------------------------------------------10-75
10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)-----------------------------------------------------------10-76
10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) -----------------------------------------------------10-77
10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------10-78
10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)--------------------------10-80
10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) --------------10-86
10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) ---------------------10-91
10.4 TIO (Input/Output-Related 16-Bit Timer) ---------------------------------------------------------------------------10-94
10.4.1 Outline of TIO ---------------------------------------------------------------------------------------------------10-94
10.4.2 Outline of Each Mode of TIO --------------------------------------------------------------------------------10-96
10.4.3 TIO Related Register Map -----------------------------------------------------------------------------------10-99
10.4.4 TIO Control Registers -----------------------------------------------------------------------------------------10-101
10.4.5 TIO Counters (TIO0CT–TIO9CT) --------------------------------------------------------------------------10-109
10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)---------------------------------------------10-110
10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ----------------------------------------------------------10-111
10.4.8 TIO Enable Control Registers -------------------------------------------------------------------------------10-112
10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes --------------------------------------------10-114
(4)
RENESAS [ RENESAS TECHNOLOGY CORP ]
