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M32180F8TFP 参数 Datasheet PDF下载

M32180F8TFP图片预览
型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Table of contents  
CHAPTER 1 OVERVIEW  
1.1 Outline of the 32180 Group ---------------------------------------------------------------------------------------------1-2  
1.1.1  
1.1.2  
1.1.3  
1.1.4  
1.1.5  
1.1.6  
M32R Family CPU Core with Built-in FPU (M32R-FPU) ---------------------------------------------1-2  
1.1.2 Built-in Multiplier/Accumulator ----------------------------------------------------------------------1-3  
Built-in Single-precision FPU --------------------------------------------------------------------------------1-3  
Built-in Flash Memory and RAM ----------------------------------------------------------------------------1-3  
Built-in Clock Frequency Multiplier -------------------------------------------------------------------------1-4  
Powerful Peripheral Functions Built-in --------------------------------------------------------------------1-4  
1.2 Block Diagram--------------------------------------------------------------------------------------------------------------1-5  
1.3 Pin Functions ---------------------------------------------------------------------------------------------------------------1-8  
1.4 Pin Assignments -----------------------------------------------------------------------------------------------------------1-14  
CHAPTER 2 CPU  
2.1 CPU Registers -------------------------------------------------------------------------------------------------------------2-2  
2.2 General-purpose Registers ---------------------------------------------------------------------------------------------2-2  
2.3 Control Registers ----------------------------------------------------------------------------------------------------------2-2  
2.3.1  
2.3.2  
2.3.3  
2.3.4  
2.3.5  
Processor Status Word Register: PSW (CR0) ----------------------------------------------------------2-3  
Condition Bit Register: CBR (CR1) ------------------------------------------------------------------------2-4  
Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)-------------------------2-4  
Backup PC: BPC (CR6) --------------------------------------------------------------------------------------2-4  
Floating-point Status Register: FPSR (CR7) ------------------------------------------------------------2-5  
2.4 Accumulator-----------------------------------------------------------------------------------------------------------------2-7  
2.5 Program Counter ----------------------------------------------------------------------------------------------------------2-7  
2.6 Data Formats ---------------------------------------------------------------------------------------------------------------2-8  
2.6.1  
2.6.2  
Data Types -------------------------------------------------------------------------------------------------------2-8  
Data Formats ----------------------------------------------------------------------------------------------------2-9  
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution -----------------2-14  
2.8 Precautions on CPU -----------------------------------------------------------------------------------------------------2-14  
CHAPTER 3 ADDRESS SPACE  
3.1 Outline of the Address Space ------------------------------------------------------------------------------------------3-2  
3.2 Operation Modes ----------------------------------------------------------------------------------------------------------3-4  
3.3 Internal ROM and Extended External Areas------------------------------------------------------------------------3-5  
3.3.1  
3.3.2  
Internal ROM Area ---------------------------------------------------------------------------------------------3-5  
Extended External Area --------------------------------------------------------------------------------------3-5  
3.4 Internal RAM and SFR Areas ------------------------------------------------------------------------------------------3-6  
3.4.1  
3.4.2  
Internal RAM Area ---------------------------------------------------------------------------------------------3-6  
SFR (Special Function Register) Area --------------------------------------------------------------------3-6  
3.5 EIT Vector Entry -----------------------------------------------------------------------------------------------------------3-35  
3.6 ICU Vector Table ----------------------------------------------------------------------------------------------------------3-36  
3.7 Notes on Address Space ------------------------------------------------------------------------------------------------3-38  
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