CPU
2.6 Data Formats
2
(7) Notes on data transfer
When transferring data, be aware that data arrangements in registers and memory are different.
Data in registers
Data in memory
• Word data (32 bits)
(R0–R15)
+0
+1
HL
+2
LH
+3
LL
HH
HL
LH
LL
b31
HH
b0
b0
b31
• Halfword data (16 bits)
(R0–R15)
+0
H
+1
L
+2
+3
H
H
L
b0
b31
b0
b15
(R0–R15)
b0
+0
+1
+2
H
+3
L
L
b31
b16
b31
• Byte data (8 bits)
(R0–R15)
+0
+1
+2
+2
+3
+3
b0
b31
b31
b0 b7
+0
(R0–R15)
b0
+1
b8 b15
(R0–R15)
b0
+0
+0
+1
+2
b16 b23
+2
+3
+3
b31
b31
(R0–R15)
b0
+1
b24 b31
Figure 2.6.9 Difference in Data Arrangements
32180 Group User’s Manual (Rev.1.0)
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