OVERVIEW
1.2 Block Diagram
1
1.2 Block Diagram
Figure 1.2.1 shows a block diagram of the 32180. The features of each block are described in Table 1.2.1.
Internal Bus
Interface
M32R-FPU Core
(80 MHz)
DMAC
(10 channels)
Multiplier/Accumulator
(32 bits × 16 bits + 56 bits)
Single-precision FPU
(fully IEEE 754 compliant)
Multijunction Timer
(64 channels)
A-D Converter × 2
(A-D0 : 10-bit converter, 16 channels)
(A-D1 : 10-bit converter, 16 channels)
Internal Flash Memory
(1 Mbytes = 1,024 Kbytes)
Serial I/O
(6 channels)
Internal RAM
(48 Kbytes)
Interrupt Controller
(32 sources, 8 levels)
Wait Controller
Real-Time Debugger
(RTD)
Full CAN
(2 channels)
PLL Clock Generator
External Bus
Interface
Internal Power Supply
Generator (VDC)
Data
Address
Input/output ports, 158 lines
Figure 1.2.1 Block Diagram of the 32180
32180 Group User’s Manual (Rev.1.0)
1-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
