Appendix 4.1 Precautions about the CPU -------------------------------------------------------------------------- Appendix 4-2
Appendix 4.1.1 Precautions Regarding Data Transfer ------------------------------------------------ Appendix 4-2
Appendix 4.2 Precautions about the Address Space ------------------------------------------------------------------ Appendix 4-3
Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------- Appendix 4-3
Appendix 4.3 Precautions about EIT ------------------------------------------------------------------------------------ Appendix 4-3
Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory -------------------------- Appendix 4-3
Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------------------- Appendix 4-4
Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------- Appendix 4-4
Appendix 4.6 Precautions about Input/Output Ports ------------------------------------------------------------------- Appendix 4-4
Appendix 4.6.1 When Using Input/Output Ports in Output Mode ----------------------------------- Appendix 4-4
Appendix 4.6.2 About the Port Input Disable Function ------------------------------------------------ Appendix 4-4
Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------------------- Appendix 4-5
Appendix 4.7.1 About Writing to the DMAC Related Registers ------------------------------------- Appendix 4-5
Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer ------------------ Appendix 4-5
Appendix 4.7.3 About the DMA Interrupt Request Status Register -------------------------------- Appendix 4-5
Appendix 4.7.4 About the Stable Operation of DMA Transfer --------------------------------------- Appendix 4-5
Appendix 4.8 Precautions about the Multijunction Timers ------------------------------------------------------------ Appendix 4-6
Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode ---------------------------- Appendix 4-6
Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode ---------------- Appendix 4-8
Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ---------------------------- Appendix 4-9
Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes ------------ Appendix 4-9
Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ------------------------------------- Appendix 4-9
Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ----------------------------- Appendix 4-9
Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode ----------------- Appendix 4-10
Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode------------------------------ Appendix 4-10
Appendix 4.8.9 Precautions on Using TMS Measure Input ------------------------------------------ Appendix 4-10
Appendix 4.8.10 Precautions on Using TML Measure Input------------------------------------------- Appendix 4-11
Appendix 4.8.11 Precautions on Using TOU PWM Output Mode ------------------------------------ Appendix 4-12
Appendix 4.8.12 Precautions on Using TOU Single-Shot PWM Output Mode -------------------- Appendix 4-12
Appendix 4.8.13 Precautions on Using TOU Delayed Single-Shot Output Mode ---------------- Appendix 4-12
Appendix 4.8.14 Precautions on Using TOU Single-Shot Output Mode ---------------------------- Appendix 4-13
Appendix 4.8.15 Precautions on Using TOU Continuous Output Mode ---------------------------- Appendix 4-13
Appendix 4.9 Precautions about the A-D Converters ---------------------------------------------------------------- Appendix 4-14
Appendix 4.10 Precautions about Serial I/O ---------------------------------------------------------------------------- Appendix 4-17
Appendix 4.10.1 Precautions on Using CSIO Mode ---------------------------------------------------- Appendix 4-17
Appendix 4.10.2 Precautions on Using UART Mode --------------------------------------------------- Appendix 4-18
Appendix 4.11 Precautions about RAM Backup Mode --------------------------------------------------------------- Appendix 4-19
Appendix 4.11.1 Precautions to Be Observed at Power-On ------------------------------------------ Appendix 4-19
Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------------------- Appendix 4-20
Appendix 4.12.1 Notes on Board Design when Connecting JTAG ---------------------------------- Appendix 4-20
Appendix 4.12.2 Processing Pins when Not Using JTAG --------------------------------------------- Appendix 4-22
Appendix 4.13 Precautions about Noise -------------------------------------------------------------------------------- Appendix 4-23
Appendix 4.13.1 Reduction of Wiring Length ------------------------------------------------------------- Appendix 4-23
Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines ------------------- Appendix 4-26
Appendix 4.13.3 Processing Analog Input Pin Wiring -------------------------------------------------- Appendix 4-26
Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin -------------------------------- Appendix 4-27
Appendix 4.13.5 Processing Input/Output Ports --------------------------------------------------------- Appendix 4-31
(11)
RENESAS [ RENESAS TECHNOLOGY CORP ]
