Table 1.3
Item
CPU
Specifications (100-Pin Package) (1/2)
Function
Central processing
unit
1. Overview
Memory
ROM, RAM, data
flash
Power Supply Voltage Detection
External Bus
Expansion
Bus/memory
expansion function
Specification
M32C/80 core (multiplier: 16 bits × 16 bits
→
32 bits
multiply-addition operation instructions: 16 × 16 + 48
→
48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V)
41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V)
• Operating mode: Single-chip mode, memory expansion mode,
and microprocessor mode
See
Tables 1.5 to 1.7 Product List.
Vdet3 detection function, Vdet4 detection function,
cold start/warm start determination function
• Address space: 16 Mbytes
• External bus interface: 1 to 7 wait states can be inserted,
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate bus and multiplexed
bus formats, switchable data bus width (8-bit or 16-bit)
• 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detection function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7
15-bit × 1 channel (with prescaler)
• 4 channels, cycle steal method
• Trigger sources: 43
• Transfer modes: 2 (single transfer and repeat transfer)
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode,
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
and timer B2)
On-chip dead time timer
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DMA
DMAC
DMACII
Timer
Timer A
Timer B
Timer function for
3-phase motor
control
Page 4 of 85
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