M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
8
8
8
4
8
8
Port P0
Port P4
Port P6
Port P2
Port P3
Port P5
(4)
System clock
generation circuit
Internal peripheral functions
Timer (16-bit)
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Output (timer A): 5
Input (timer B): 6
UART or
clock synchronous serial I/O (2 channels)
UART (1 channel)
(3)
Clock synchronous serial I/O
(8 bits X 2 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Memory
ROM (1)
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R0L
R1L
SB
USP
ISP
R2
R3
DMAC
(2 channels)
RAM (2)
INTB
PC
FLG
A0
A1
FB
D/A converter
(8 bits X 2 channels)
Multiplier
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Figure 1.2
M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Rev.2.41 Jan 10, 2006 Page 6 of 96
REJ03B0001-0241
RENESAS [ RENESAS TECHNOLOGY CORP ]
