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M3062LFGPFP 参数 Datasheet PDF下载

M3062LFGPFP图片预览
型号: M3062LFGPFP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 101 页 / 1125 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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M16C/62P Group (M16C/62P, M16C/62PT)  
5. Electrical Characteristics  
(1)  
Table 5.4  
A/D Conversion Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Measuring Condition  
Min.  
Typ.  
Max.  
10  
Resolution  
VREF=VCC1  
Bits  
INL  
Integral Non-Linearity  
Error  
10bit  
VREF= AN0 to AN7 input,  
VCC1= AN0_0 to AN0_7 input,  
±3  
LSB  
5V  
AN2_0 to AN2_7 input,  
ANEX0, ANEX1 input  
External operation amp  
connection mode  
±7  
±5  
LSB  
LSB  
VREF= AN0 to AN7 input,  
VCC1= AN0_0 to AN0_7 input,  
3.3V  
AN2_0 to AN2_7 input,  
ANEX0, ANEX1 input  
External operation amp  
connection mode  
±7  
LSB  
8bit  
VREF=VCC1=5V, 3.3V  
±2  
±3  
LSB  
LSB  
Absolute Accuracy  
10bit  
VREF= AN0 to AN7 input,  
VCC1= AN0_0 to AN0_7 input,  
5V  
AN2_0 to AN2_7 input,  
ANEX0, ANEX1 input  
External operation amp  
connection mode  
±7  
±5  
LSB  
LSB  
VREF= AN0 to AN7 input,  
VCC1 AN0_0 to AN0_7 input,  
=3.3V AN2_0 to AN2_7 input,  
ANEX0, ANEX1 input  
External operation amp  
connection mode  
±7  
±2  
LSB  
8bit  
VREF=VCC1=5V, 3.3V  
LSB  
kΩ  
Tolerance Level Impedance  
Differential Non-Linearity Error  
Offset Error  
3
DNL  
±1  
±3  
±3  
40  
LSB  
LSB  
LSB  
kΩ  
Gain Error  
RLADDER  
tCONV  
Ladder Resistance  
VREF=VCC1  
10  
10-bit Conversion Time, Sample & Hold  
Available  
VREF=VCC1=5V, φAD=12MHz  
2.75  
µs  
tCONV  
8-bit Conversion Time, Sample & Hold  
Available  
VREF=VCC1=5V, φAD=12MHz  
2.33  
µs  
tSAMP  
VREF  
VIA  
Sampling Time  
0.25  
2.0  
0
µs  
V
Reference Voltage  
Analog Input Voltage  
VCC1  
VREF  
V
NOTES:  
1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = 20 to 85°C / 40 to 85°C unless otherwise specified.  
2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.  
3. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less.  
4. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 3.  
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 3.  
Rev.2.41 Jan 10, 2006 Page 43 of 96  
REJ03B0001-0241  
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