M16C/62 Group (M16C/62P, M16C/62PT)
1. Overview
1.2 Performance Outline
Table 1.1 to table 1.3 list performance outline of M16C/62 group (M16C/62P, M16C/62PT).
Table 1.1 Performance outline of M16C/62 group (M16C/62P) (128-pin version)
Item
CPU
Number of basic instructions
Shortest instruction execution time
Operation mode
Memory space
Memory capacity
Port
Multifunction timer
Serial I/O
Performance
M16C/62P
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion and microprocessor mode
1 Mbyte (Available to 4M bytes by memory space
expansion function)
See
table 1.4 and 1.5 Product List
Input/Output : 113 pins, Input : 1 pin
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels
Three phase motor control circuit
3 channels
Clock synchronous, UART,
I
2
C bus
(1)
, IEBus
(2)
2 channels
Clock synchronous
10-bit A-D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
Ring oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Stop detection of main clock oscillation
,
re-oscillation detection
function
Available (option
(4)
)
VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8
µA
(VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7
µ
A (VCC1=VCC2=3V, stop mode)
3.3
±
0.3 V or 5.0
±
0.5 V
100 times (all area)
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
(3)
–20 to 85
o
C
–40 to 85
o
C
(3)
128-pin plastic mold QFP
Peripheral
function
A-D converter
D-A converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock generating circuit
Oscillation stop detection function
Voltage detection circuit
Supply voltage
Power consumption
Electric
characteris-
tics
Flash memory
Version
Program/erase supply voltage
Program and erase endurance
Operating ambient temperature
Package
NOTES:
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
table 1.8 Product Code
for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.
4. All options are on request basis.
Rev.2.10 Nov. 07, 2003 page 2
of 84
RENESAS [ RENESAS TECHNOLOGY CORP ]
