ISL6614
the SO14 package is approximately 1W at room temperature,
while the power dissipation capacity in the QFN packages, with
an exposed heat escape pad, is around 2W. See “Layout
Considerations” on page 10 for thermal transfer improvement
suggestions. When designing the driver into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses due to the gate
charge of MOSFETs and the driver’s internal circuitry and their
corresponding average driver current can be estimated using
Equations 2 and 3, respectively:
PVCC
BOOT
D
C
GD
R
HI1
G
C
DS
R
R
LO1
R
GI1
C
G1
GS
Q1
S
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
(EQ. 2)
P
= 2 P
+ 2 P
+ I VCC
Qg_Q2 Q
Qg_TOT
Qg_Q1
2
Q
PVCC
G1
--------------------------------------
P
=
=
F
N
Qg_Q1
SW
Q1
V
GS1
PVCC
D
2
Q
PVCC
G2
--------------------------------------
P
F
N
Qg_Q2
SW
Q2
C
V
GD
GS2
R
HI2
G
C
DS
R
R
LO2
R
GI2
C
G2
Q
N
Q
N
Q2
V
GS2
G1
V
Q1
G2
----------------------------- -----------------------------
I
=
+
F
2 + I
SW Q
DR
GS
Q2
GS1
S
(EQ. 3)
where the gate charge (Q and Q ) is defined at a particular
G1
G2
and V
gate to source voltage (V
) in the corresponding
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
GS1
GS2
MOSFET datasheet; I is the driver’s total quiescent current
Q
with no load at both drive outputs; N and N are number of
upper and lower MOSFETs, respectively; PVCC is the drive
voltages for both upper and lower FETs, respectively. The
Q1 Q2
Layout Considerations
For heat spreading, place copper underneath the IC whether it
has an exposed pad or not. The copper area can be extended
beyond the bottom area of the IC and/or connected to buried
copper plane(s) with thermal vias. This combination of vias for
vertical heat escape, extended copper plane, and buried
planes for heat spreading allows the IC to achieve its full
thermal potential.
I
VCC product is the quiescent power of the driver without
Q*
capacitive load and is typically 200mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate resistors
Place each channel power component as close to each other
as possible to reduce PCB copper losses and PCB parasitics:
shortest distance between DRAINs of upper FETs and
SOURCEs of lower FETs; shortest distance between DRAINs
of lower FETs and the power ground. Thus, smaller amplitudes
of positive and negative ringing are on the switching edges of
the PHASE node. However, some space in between the power
components is required for good airflow. The traces from the
drivers to the FETs should be kept short and wide to reduce the
inductance of the traces and to promote clean drive signals.
(R and R ) and the internal gate resistors (R
G1 G2
and R )
GI2
GI1
of MOSFETs. Figures 3 and 4 show the typical upper and
lower gate drives turn-on transition path. The power dissipation
on the driver can be roughly estimated as:
P
= 2 P
+ 2 P
+ I VCC
Q
(EQ. 4)
DR
DR_UP
R
DR_LOW
R
P
Qg_Q1
HI1
LO1
-------------------------------------- --------------------------------------- ---------------------
P
=
+
DR_UP
R
+ R
R
+ R
EXT1
2
HI1
EXT1
LO1
R
R
P
Qg_Q2
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
DR_LOW
R
+ R
R
+ R
EXT2
2
HI2
EXT2
LO2
R
R
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
EXT1
G1
EXT2
N
N
Q1
Q2
FN9155 Rev.5.00
May 5, 2008
Page 10 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
