HM62V8512C Series
Write Cycle
HM62V8512C
-5
Parameter
Write cycle time
Chip selection to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time
WE
to output in high-Z
Data to write time overlap
Data hold from write time
Output active from output in high-Z
Output disable to output in high-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
Min
55
50
0
50
40
0
0
25
0
5
0
Max
—
—
—
—
—
—
20
—
—
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
1, 2, 7
3, 12
6
1, 2, 7
4
5
Notes
Notes: 1. t
HZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
WP
) of a low
CS
and a low
WE.
A write begins at the later
transition of
CS
going low or
WE
going low. A write ends at the earlier transition of
CS
going high
or
WE
going high. t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from
CS
going low to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
WR
is measured from the earlier of
WE
or
CS
going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the
CS
low transition occurs simultaneously with the
WE
low transition or after the
WE
transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If
CS
is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem of
data bus contention. t
WP
≥
t
DW
min + t
WHZ
max
8
RENESAS [ RENESAS TECHNOLOGY CORP ]
