HM628512C Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol Min
Typ Max
Unit
V
Test conditions*3
VCC for data retention
Data retention current
VDR
2
—
—
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
ICCDR
—
0.8*4 20*1
µA
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
—
0.8*4 10*2
µA
ns
ns
Chip deselect to data retention time tCDR
Operation recovery time tR
0
tRC*5
—
—
—
—
See retention waveform
Notes: 1. For L-version and 10 µA (max.) at Ta = –20 to +40°C.
2. For L-SL-version and 3 µA (max.) at Ta = –20 to +40°C.
3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS Controlled)
tR
tCDR
Data retention mode
VCC
4.5 V
2.2 V
VDR
CS
0 V
CS ≥ VCC – 0.2 V
12
RENESAS [ RENESAS TECHNOLOGY CORP ]
