HIP6601B, HIP6603B, HIP6604B
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated by
the driver is approximated as:
3
-
P
=
1.05f
sw
--
V
U
Q
+
V
L
Q
+
I
DDQ
VCC
2
L
U
(EQ. 2)
0.15F
HIP660X
VCC
0.15F
PWM
Test Circuit
+5V OR +12V
+12V
+5V OR +12V
0.01F
BOOT
2N7002
UGATE
PHASE
LGATE
2N7002
C
L
100k
C
U
PVCC
where f
sw
is the switching frequency of the PWM signal. V
U
and V
L
represent the upper and lower gate rail voltage. Q
U
and
Q
L
is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to the
gate pins. The I
DDQ
V
CC
product is the quiescent power of the
driver and is typically 30mW.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip during
the refresh cycle. Expressing this power in terms of the upper
MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or its
body diode conducts and pulls the PHASE node toward GND.
While the bootstrap device conducts, a current path is formed
that refreshes the bootstrap capacitor. Since the upper gate is
driving a MOSFET, the charge removed from the bootstrap
capacitor is equivalent to the total gate charge of the MOSFET.
Therefore, the refresh power required by the bootstrap
capacitor is equivalent to the power used to charge the gate
capacitance of the MOSFET.
1
1
-
-
P
REFRESH
= --
f
SW
Q
V
= --
f
SW
Q V
LOSS PVCC
U U
2
2
(EQ. 3)
POWER (mW)
GND
1000
C
U
= C
L
= 3nF
800
600
C
U
= C
L
= 2nF
400
200
C
U
= C
L
= 1nF
C
U
= C
L
= 4nF
C
U
= C
L
= 5nF
0
500
1000
FREQUENCY (kHz)
VCC = PVCC = 12V
1500
2000
FIGURE 1. POWER DISSIPATION vs FREQUENCY
1000
where Q
LOSS
is the total charge removed from the bootstrap
capacitor and provided to the upper gate load.
The 1.05 factor is a correction factor derived from the following
characterization. The base circuit for characterizing the drivers
for different loading profiles and frequencies is provided. C
U
and
C
L
are the upper and lower gate load capacitors. Decoupling
capacitors [0.15F] are added to the PVCC and VCC pins. The
bootstrap capacitor value is 0.01F.
In Figure 1, C
U
and C
L
values are the same and frequency is
varied from 50kHz to 2MHz. PVCC and VCC are tied together
to a +12V supply. Curves do exceed the 800mW cutoff, but
continuous operation above this point is not recommended.
Figure 2 shows the dissipation in the driver with 3nF loading on
both gates and each individually. Note the higher upper gate
power dissipation which is due to the bootstrap device refresh
cycle. Again PVCC and VCC are tied together and to a +12V
supply.
POWER (mW)
VCC = PVCC = 12V
800
C
U
= C
L
= 3nF
600
C
U
= 3nF
C
L
= 0nF
400
C
U
= 0nF
C
L
= 3nF
200
0
500
1000
FREQUENCY (kHz)
1500
2000
FIGURE 2. 3nF LOADING PROFILE
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate capacitors are
varied from 1nF to 5nF. VCC and PVCC are tied together and to a
+12V supply. Figures 4, 5 and 6 show the same characterization
for the HIP6603B with a +5V supply on PVCC and VCC tied to a
+12V supply.
Since both upper and lower gate capacitance can vary,
Figure 8 shows dissipation curves versus lower gate capacitance
with upper gate capacitance held constant at three different
values. These curves apply only to the HIP6601B due to power
supply configuration.
FN9072 Rev 9.00
December 10, 2015
Page 9 of 14
RENESAS [ RENESAS TECHNOLOGY CORP ]
