HD74LS259
Pin Arrangement
A
Latch
Select
B
C
Q
0
Q
1
Outputs
Q
2
Q
3
GND
1
A
2
3
4
5
6
7
8
B
C
Q
0
Q
1
Q
2
Q
3
Q
4
CLR
G
D
Q
7
Q
6
Q
5
16
15
14
13
12
11
10
9
V
CC
Clear
Enable
Data Input
Q
7
Q
6
Outputs
Q
5
Q
4
(Top view)
Function Table
Input
CLR
H
H
L
L
G
L
H
L
H
Output of
addressed latch
D
Qio
D
L
Select inputs
Each other output
Qio
Qio
L
L
Function
Addressable latch
Memory
8-line demultiplexer
Clear
Latch addressed
C
B
A
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
Notes: 1. H; high level, L; low level
2. D; the level at the data input
3. O
io
; the level of Q
i
(i = 0, 1,
…
7, as appropriate) before the indicated steady state input conditions were
established.
Rev.2.00, Feb.18.2005, page 2 of 7
RENESAS [ RENESAS TECHNOLOGY CORP ]
