HD74LS174 / HD74LS175
Pin Arrangement
HD74LS174
HD74LS175
Clear
1Q
1D
2D
2Q
3D
3Q
GND
1
2
3
4
5
6
7
8
Q
CLR
D CK
Q
CLR
CK D
16
15
14
13
12
11
10
9
V
CC
6Q
6D
5D
5Q
4D
4Q
Clock
Clear
1Q
1Q
1D
2D
2Q
2Q
GND
1
2
3
4
5
6
7
8
Q
D
CK
Q
CLR
Q
D
CK
CLR
Q
Q
CLR
CK
Q
D
CLR
Q
CK
D
Q
16
15
14
13
12
11
10
9
V
CC
4Q
4Q
4D
3D
3Q
3Q
Clock
D CK
CLR
Q
CK D
CLR
Q
D CK
CLR
Q
CK D
CLR
Q
(Top view)
(Top view)
Function Table
Clear
L
H
H
H
Notes: 1.
2.
3.
4.
Inputs
Clock
X
↑
↑
L
Outputs
D
X
H
L
X
Q
L
H
L
Q
0
Q
H
L
H
Q
0
H; high level, L; low level, X; irrelevant
↑;
transition from low to high level
Q
0
; the level of Q before the indicated steady-state input conditions were established.
Q
is applied to HD74LS175 only.
Rev.3.00, Jul.15.2005, page 2 of 8