HD74LV74A
Dual D–type Flip Flops with Preset and Clear
REJ03D0312–0300Z
(Previous ADE-205-244A (Z))
Rev.3.00
Jun. 02, 2004
Description
The HD74LV74A has independent data, preset, clear, and clock inputs Q and
Q
outputs in a 14 pin package. The input
data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed operation is
suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the
battery life.
Features
•
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–14 pin(JEITA)
SOP–14 pin(JEDEC)
TSSOP–14 pin
Package Code
FP–14DAV
FP–14DNV
TTP–14DV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV74AFPEL
HD74LV74ARPEL
HD74LV74ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
↓
D
X
X
X
H
L
X
Outputs
Q
H
L
H*
1
H
L
Q
0
Q
L
H
H*
1
L
H
Q
0
Note: H: High level
L: Low level
X: Immaterial
↑:
Low to high transition
↓:
High to low transition
Q
0
: The level of Q immediately before the input conditions shown in the above table is determined.
1.: Q and
Q
will remain HIGH as long as Preset and Clear are Low, but Q and
Q
are unpredictable, if Preset
and Clear go HIGH simultaneously.
Rev.3.00 Jun. 02, 2004 page 1 of 9
RENESAS [ RENESAS TECHNOLOGY CORP ]
