HD74HCT373, HD74HCT533
Octal D-type Transparent Latches (with 3-state outputs)
Octal D-type Transparent Latches (with inverted 3-state outputs)
REJ03D0666–0200
(Previous ADE-205-555)
Rev.2.00
Mar 30, 2006
Description
When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of
HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals present at the other inputs and the state of the
storage elements.
Features
•
•
•
•
•
•
•
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(Data to Q) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
HD74HCT373P
HD74HCT373FPEL
HD74HCT373RPEL
HD74HCT533RPEL
HD74HCT373TELL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC)
TSSOP-20 pin
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
PRSP0020DC-A
(FP-20DBV)
PTSP0020JB-A
(TTP-20DAV)
Package
Abbreviation
P
FP
RP
T
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
D
Output Control
Enable G
L
H
H
L
H
L
L
L
X
H
X
X
Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
HD74HCT373
Q
H
L
No change
Z
HD74HCT533
Q
L
H
No change
Z
Rev.2.00 Mar 30, 2006 page 1 of 8
RENESAS [ RENESAS TECHNOLOGY CORP ]
